1. Field of the Invention
The present invention relates to the field of Sublithographic fabrication of electronic circuits. More specifically, methods and apparatus for controlling electric conduction on nanoscale wires from both lithographic wires and nanoscale wires are disclosed, such as a stochastic assembly of sublithographic nanoscale interfaces and a sublithographic nanoscale memory architecture.
2. Description of the Prior Art
Technologies to build nanoscale crosspoints are already known. FIG. 1 is a schematic cross-sectional view which shows a suspended prior art nanotube conductor 1 coupled to a plurality of lower carbon nanotube or silicon nanoscale wire conductors 2, 3, and 4 separated by a plurality of supports 5. The supports are made of a dielectric material, such as silicon dioxide. In this way, a nanotube-nanotube (or nanotube-nanoscale wire) junction is formed. The junction is bistable with an energy barrier between the two states. In one state, see tubes 1-2 and 1-4, the tubes are “far” apart and mechanical forces keep the top wire 1 from descending to the lower wire 2, 4. At this distance the tunneling current between the crossed conductors is small, resulting, effectively, in a very high resistance (GigaOhms) between the conductors. In the second state, see tubes 1-3, the tubes come into contact or near contact and are held together via molecular forces. In this state, there is little resistance (about 100 KΩ) between the tubes. By applying a voltage between tubes, one can charge them to the same or opposite polarities and use electrical charge attraction/repulsion to cross the energy gap of the junction between the two bi-stable states, effectively setting or resetting the programming of the connection. These junctions can be rectifying such that the connected state exhibits PN-diode rectification behavior. Molecular electronics PN-junctions are disclosed, for example, in Y. Cui and C. M. Lieber, “Functional Nanoscale Electronic Devices Assembled using Silicon Nanoscale wire Building Blocks,” Science 291, 851-853 (2001).
Techniques for storing non-volatile memory bits at the crosspoints of a nanoscale wire array are already known in the art. See, for example, C. P. Collier, E. W. Wong, M. Belohradsky, F. M. Raymo, J. F. Stoddard, P. J. Kuekes, R. S. Williams, and J. R. Heath, “Electronically configurable molecular-based logic gates,” Science, vol. 285, pp.391-394, 1999. Bits can typically be programmed by placing a large voltage across individual crosspoint junctions. The status of each crosspoint is read by observing the current flowing through a junction. Programmed “ON” junctions will act as low resistance paths, while programmed “OFF” junctions will act as high resistance paths.
Also known in the prior art is how doped silicon nanoscale wires can exhibit Field-Effect Transistor (FET) behavior. FIG. 2 is a schematic perspective view of a prior art embodiment which shows oxide 10 grown over a silicon nanoscale wire 11 to prevent direct electrical contact of a crossed conductor 12, for example a carbon nanotube or a silicon nanoscale wire. The electrical field of one wire can then be used to “gate” the other wire, locally evacuating a region of the doped silicon nanoscale wire of carriers to prevent conduction. FET resistance varies from Ohms to GigaOhms. Similarly, also carbon nanotubes can exhibit FET behavior. See, for example, Yu Huang, Xiangfeng Duan, Yi Cui, Lincoln Lauhon, Kevin Kim and Charles M. Lieber, “Logic Gates and Computation from Assembled Nanoscale wire Building Blocks,” Science, 2001, v294, p1313-1317, V. Derycke, R. Martel, J. Appenzeller and Ph. Avouris, “Carbon Nanotube Inter- and Intramolecular Logic Gates,” Nano Letters, 2001,v1n9, p435-456, and Sander J. Trans, Alwin R. M. Verschueren and Cees Dekker, “Room-temperature Transistor Based on a Single Carbon Nanotube,” Nature, 1998, v393, p49-51, May 7.
The doping profile or material composition along the axial dimension of a nanoscale wire can be controlled, as shown in Mark S. Gudiksen, Lincoln J. Lauhon, Jianfang Wang, David C. Smith, and Charles M. Lieber, “Growth of nanowire superlattice structures for nanoscale photonics and electronics,” Nature, v415 p617-620, February 2002, Yiying Wu, Rong Fan, and Peidong Yang, “Block-by-block growth of single-crystalline Si/SiGe superlattice nanowires,” Nano Letters, v2 n2, p83-86, February 2002, and M. T. Bjork, B. J. Ohlsson, T. Sass, A. I. Persson, C. Thelander, M. H. Magnusson, K. Depper, L. R. Wallenberg, and L. Samuelson, “One-dimensional steeplechase for electrons realized,” Nano Letters, v2 n2, p87-89, February 2002.
Furthermore, regular arrangements of nanoscale wires (parallel arrays of wires, crossed, orthogonal structures) are also known. A crossbar is usually defined as an array of switches that connect each wire in one set of parallel wires to every member of a second set of parallel wires that intersects the first set. Generally, the two sets of wires are perpendicular to each other. In the “on” position the switch connects the horizontal wire to the vertical wire, while in the “off” position the two wires remain disconnected. As a consequence, it is possible to store the switch state and implement switching in the area of a crosspoint. That is, the switch device itself holds its state. Therefore, crossbars in this technology can be fully populated with no cost in density. This is particularly beneficial in achieving the necessary defect tolerance. See, for example, U.S. Pat. No. 6,256,767 to Kuekes, Williams and Stanley.
Further, non-volatile memories can be built which are as tight as the nanoscale (sublithographic) wire pitch. See, for example, U.S. Pat. No. 6,128,214 to Kuekes, Williams, Stanley and Heath.
However, in order to program or read these crosspoint, a way to apply a control voltage to an individual nanoscale wire and to selectively read from a single nanoscale wire is needed. Therefore, a critical weak link in the construction of fully nanoscale memory and logic arrays is the construction of an interface that allows one to individually address the nanoscale wires from the microscale wires.
A scheme for bridging the microscale-nanoscale gap with a decoder based on randomly deposited gold nanoparticles has been disclosed in U.S. Pat. No. 6,256,767 cited above. The gold particles must be deposited over the region in which control and address wires intersect. This prior art approach relies on close control of the density of deposited particles, ideally targeting half of the points of intersection. Additionally, the approach relies on strongly quantized connection values for each intersection, while imprecisely localized gold nanoparticles could lead to intermediate values that complicate the discovery of wires that are connected. Consequently, the prior art approach comes with its own set of manufacturing challenges.
Therefore, a better way to individually address the nanoscale wires is needed. The present disclosure shows devices and methods able to control single nanoscale wires individually, wherein control is performed both at the microscale level and at the nanoscale level, so that individual crosspoints can be programmed and addressed.
Throughout the present disclosure, the term micron-scale (also microscale) will refer to dimensions that range from about 0.1 micrometer to about 2 micrometers in size. The term nanometer-scale (also nanoscale) will refer to dimensions that range from 0.1 nanometers to 50 nanometers (0.05 micrometer), the preferred range being from 0.5 nanometers to 5 nanometers.